Solution

Guardband Recovery

Guardbands are set once, for the slowest silicon at the worst-case corner, because that is the only device a vendor can guarantee. Once every device is monitored in-system and its defects are exposed, Fluid Silicon recovers the excess guardband as lower power and, where a workload needs it, performance. Reliability comes first: the margin you specify stays in place, and nothing runs past what the measurement supports.

An FPGA accelerator card, drawn in isometric view

Measured impact

On production shells, at realistic utilization.

30–54%
timing margin carried today for the worst-case corner*
< 20 ps
per-link resolution; the margin you keep covers measurement error plus drift
1 s
to re-measure every logic element after a change

*Fluid Silicon measurements. Varies with variation pattern, workload, vendor and device age.

Adaptive Voltage Scaling

Lower power without giving up margin.

  • Vccint set from timing measured on that device, not a family datasheet.
  • Margin held for measurement error and drift until the next sweep; each link is resolved to under 20 ps.
  • Every change scheduled, handshake-gated and re-measured within a second.
  • One policy on AMD and Altera devices.
  • Read-only first: the recommended operating point is visible before anything moves.

Worked example

10,000 cards at 75 W in a facility with a PUE of 1.2: every 1% of card power is about 79 MWh a year at the wall. The reduction available depends on the margin your devices carry today.

One card's recommended operating point, waiting for approval. Illustrative screen.

Adaptive Frequency Scaling

The clock follows measured margin.

  • Sustainable clock measured per device over long periods, not a one-time lab figure.
  • Aging models lower the clock before a device drifts out of margin.
  • Any increase is opt-in, in your maintenance windows, with a handshake on every device.
  • Monitoring continues after every change.

Guardrails

The clock moves only inside measured margin, and only by the amount that leaves your specified slack in place. A device aging toward its threshold is brought down before it reaches it.

A margin per chip instead of one for the fleetThree chips measured separately, each with narrow distributions of LUT and carry link delays, and each signed off at its own measured delay plus under 20 picoseconds of error and drift. The fleet-wide worst-case corner is shown faintly on the right, no longer needed.Measured: a margin per chipFleet corner, no longer neededChip AChip BChip CPer-chip margin: error + drift, under 20 psPath delay →
LUT linksCarry linksPer-chip sign-off
Illustrative, not to scale.

Per-Device Sign-off

One margin per device.

  • Each device's path-delay distribution, measured link by link.
  • Sign-off margin: measurement error plus drift, with each link resolved to under 20 ps.
  • Measuring more devices finds more tails; it adds no margin to the devices without them.
  • The same sign-off from 28 nm to 10 nm class.

Why every device carries margin today

A vendor must guarantee timing for every device it ships, so its model describes the worst one: defective, hot, at elevated voltage, at end of life. That is the right call for a vendor. It also means every device you run carries that one's guardband.

An FPGA accelerator card, drawn in isometric view

Operating-Point Policy

One device, one board or the whole fleet.

  • Operating points coordinated per device, per board or fleet-wide.
  • Your thresholds, your windows, your approvals.
  • Telemetry in one vendor-neutral schema, into your existing monitoring.
  • Nothing is applied without a handshake.

Read-only first

Monitoring and modeling never change an operating point. Voltage and frequency scaling are separate steps enabled by policy, and you can stop at any step.

An FPGA accelerator card, drawn in isometric view

FAQ

Common questions.

Sensor architecture, deployment mechanics and calibration methods are shared with evaluation partners under NDA.

Is this overclocking?

No. The goal is reliability. Every device is kept inside the timing margin measured on that device, with your specified slack in place, and the operating point is pulled back as it ages. Energy and performance are what the worst-case guardband no longer has to hold back.

How much power can we save?

It depends on the margin each device carries today, which we measure before recommending anything. The worked example shows the arithmetic; an evaluation on a few of your boards shows your number.

Does tuning put timing at risk?

Margin is kept for measurement error plus drift, every change is re-measured within a second, and aging models pull the operating point back before a device drifts toward the threshold. Every change is scheduled and handshake-gated.

Can we run voltage and frequency scaling together?

Yes. Both read the same measurements. Most deployments start with voltage, which lowers power without changing throughput, and change frequency only where a workload needs it and the measured margin allows.

Which devices are supported?

AMD 7-series, UltraScale and UltraScale+ today, with select Altera Agilex 7 devices. Stratix 10, Arria 10 and Versal AI Core are in development. See device support.

Does it change our design?

Your RTL is not changed. The health layer occupies a small region reserved beside your design, planned with your team during evaluation, and needs no JTAG exposure.

What does it cost in area and delay?

Under 1% of LUTs and under 5% of flip-flops on a production shell, under 2% delay impact, and no downtime to monitor.

How does this relate to facility energy?

Card power is paid for again in cooling and distribution, which is what PUE captures. Whatever you save on the card is multiplied at the wall.

Is the margin you sign off the margin we keep?

Yes. The measurement made at qualification continues in production, so the margin is checked for the life of the device rather than assumed once.

Measure a device at speed, live.

A 30-minute session: in-system slack measurements on a supported AMD or Altera device, and what an evaluation on your boards involves.