About Fluid Silicon
We build in-system timing measurement for the engineers who run critical FPGA systems: which device is losing margin, where on the die, and how long it has left, so they act in a maintenance window instead of after a failure.
The idea
Every chip is engineered once, for a worst-case scenario, then run that way for its entire life, regardless of how it actually performs once deployed. That is a reasonable approach given what has been possible to measure in the field. But as transistors shrink, the gap between how a chip was designed and how it actually behaves keeps widening, and it gets harder to see.
What we build
A small region beside your design that measures the timing of every logic element while the chip runs, so the chip can report its own condition. How it works
What it changes
How much margin each device has, where it is weak, how fast it is aging and when it will need attention, measured rather than assumed.
Where it runs today
Families from 28 nm to 10 nm class, integrated through each vendor's own flow, deployed on your site. Device support
Team
The approach comes from reconfigurable-computing research at the University of Pennsylvania.
Nhlanhla developed the approach behind Fluid Silicon through master's research at the University of Pennsylvania on online health monitoring and runtime repair for commercial FPGAs.
André has worked in reconfigurable computing for decades, at Berkeley, Caltech and, since 2006, the University of Pennsylvania, where he is the Oliver C. Boileau Jr. and Nan Eleze Boileau Professor of Electrical Engineering. His research on FPGA architecture and interconnect underpins Fluid Silicon's approach.
Victor works with the founders on Fluid Silicon's business strategy, its engagement with customers, partners and funders, and the financial analysis behind those decisions. He studied economics at the Wharton School and spent two summers at Boston Consulting Group before joining.
Recognition
The University of Pennsylvania awarded Nhlanhla Mavuso its 2026 President's Sustainability Prize for Fluid Silicon, one of the largest awards of its kind in higher education.
Fluid Silicon's adaptive approach to chip performance exemplifies Penn's strength in applied innovation and offers a scalable path to greater efficiency and sustainability.
Where we're headed
Fluid Silicon has demonstrated its technology on real commercial FPGAs. The next phase is putting it to work wherever chips have to be trusted, and growing the technical team to get there.
Per-element measurement on AMD and Altera parts already in production. Evaluations start read-only, on a sample of your cards.
The full loop, monitor, model, tune and repair, deployed across data centers, aerospace and defense, telecommunications and the other industries where reliability and performance matter most.
A chip that reports its own condition is useful wherever silicon has to be trusted. FPGAs are the first place it can be added without new silicon; they are the first step, not the last.
Partners and ecosystem
The health layer integrates through each vendor's own toolchain: AMD Vivado for AMD parts, Altera Quartus for Altera parts. Fluid Silicon is not affiliated with or endorsed by either vendor; product names are their trademarks.
Devices
AMD 7-series, UltraScale and UltraScale+ supported today, with select Altera Agilex 7 devices. Stratix 10, Arria 10 and Versal AI Core are in development. Device support
Research
Fluid Silicon grew out of reconfigurable-computing research at Penn. Research collaborations on variation, aging and reliability are welcome.
Partner program
Board and system makers, cloud and infrastructure operators, systems integrators, EDA and tool vendors, and aerospace and defense primes. Every partnership starts with a technical session and an evaluation on real hardware. Talk to us
How we work
A number measured on your chip is worth more than a guardband set for someone else's. Margin should cover measurement error, not uncertainty.
Every logic element, at speed, in production, with no downtime.
Replacements, upgrades and retirements rest on data from the card itself.
Nothing changes on a production system without your approval.
One health metric that means the same thing on every part you run.
Where we are
One office, one bench, near the university where the research began.
Fluid Silicon is based in Philadelphia, close to the University of Pennsylvania, where the research behind the platform began.
The University of Pennsylvania on the research behind Fluid Silicon and the President's Sustainability Prize awarded to Nhlanhla Mavuso for the project.
Penn TodayApril 2026Penn announces its 2026 prize recipients. The Sustainability Prize recognizes the work behind Fluid Silicon: running chips at their measured limits instead of a worst-case margin.
Penn TodayFPGA and systems engineers, and interns, in Philadelphia. We reply to every application within five business days.